In Delay Fault Testing

Testing and design for testability are critical steps in the process of building reliable electronic circuits. This dissertation contributes t o improving the quality of d e l a y faul t t e s t ing: testing for manufacturing faults that result in delays beyond circuit specifications. It highlights the importance of considering electrical phenomena when developing techniques for identifying delay faults. Previous research in delay fault testing has not considered such phenomena, and we show that when they axe disre* garded, faulty circuits can be declared fault-free. Our results have many implications for this field and re-open numerous problems. In this dissertation, we lay a new I foundation for delay fault testing: We demonstrate tha t a basic, often implicit assumption underlying research in delay fault testing is invalid due to circuit electrical phenomena. We identify three delay effects that cause this invalidation and we develop gate-levGl guidelines to account for these effects. 0 We show that our findings have'a profound impact on concepts and techniques used in delai fault testing. In particular, they necessitate a revision of the delay test definition and of the criteria for test quality evaluation, both of which are fundamental in delay test procedures and techniques. 0 We present constructive solutions to some of the problems that result from our findings. These include a method for estimating ranges of path delays, and an algorithm for eliminating through circuit transformations one of the delay ' effects we identified. Our findings regarding delay modeling, as well as the method for estimating path dehays, are applicable not only t o delay fault testing, but also t o timing analysis. Dedicated t o my parents Maria and Janusz with love and gratitude